1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a phase splitter for receiving a clock signal and for providing clock signals of similar and opposite phases when compared to the received clock signal at the same time.
2. Discussion of the Related Art
The clock signal, when used as a driving signal for a system, should have a high frequency for driving the system faster. However, since clock signal frequencies are limited, two clock signals are sometimes jointly used as a received clock signal clk_in to increase system speed, i.e., a clock signal clk having a phase equal to the received clock signal clk_in and a clock signal clk_b having a phase that is inverted with respect to the received clock signal clk_in. A background art phase splitter conventionally used to achieve these joint clock signals will be explained with reference to the attached drawings.
FIG. 1 illustrates the background art phase splitter.
Referring to FIG. 1, the background art phase splitter is provided with a first inverter 11 for inverting a phase of a received signal, a second inverter 12 for inverting an output of the first inverter 11 to provide a clock signal having a phase equal to the received signal at the end, a third inverter 13 for inverting a phase of the received signal, a fourth inverter 14 for inverting an output of the third inverter 13, and a fifth inverter 15 for inverting an output of the fourth inverter 14 to provide a clock signal having a phase opposite to the received signal. Each of the inverters has a PMOS transistor and an NMOS transistor.
The operation of the aforementioned background art phase splitter will be explained with reference to the timing diagram of FIG. 2. There is a delay, as much as td1, from reception of a clock signal clk_in to an output of a clock signal clk having the same phase. That is, the received clock signal clk_in is phase inverted by the first inverter 11 and phase inverted again by the second inverter 12. Accordingly, though a signal from the second inverter 12 has a phase equal to the received clock signal, there is a delay of as much as td1 caused by the first and second inverters 11 and 12. On the other hand, there is a delay of as much as td2 between reception of the clock signal clk_in to an output of an inverted clock signal clk_b. That is, the received clock signal clk_in is phase inverted by the third inverter 13, inverted a second time by the fourth inverter 14, and inverted a third time by the fifth inverter 15. At the end, the clock signal clk_b has an inverted phase and a delay of as much as td2 with respect to the received clock signal clk_in. Thus, the background art phase splitter provides a clock signal having a phase equal to a received clock signal and a clock signal having a phase opposite to the received clock signal using inverters.
However, the background art phase splitter has at least the following problems.
The two clock signals, i.e., clk and clk_b have a timing mismatch of as much as td2. Even if sizes of transistors in the inverters are adjusted to take the timing mismatch into consideration, the timing mismatch is still likely to exist due to variations of a fabrication process or variations of a voltage and temperature.
Moreover, conventional phase splitters divided an input clock signal clk_in into two signals, a first clock signal clk having a phase equal to the input clock signals clk_in, and a second clock signal clk_b having a phase that is opposite to the input clock signal clk_in as shown in FIG. 1, and even numbered series arrangement of inverters was used to generate first clock signal clk, while an odd numbered series arrangement of inverters was used to generate second clock signal clk_b. Because each inverter introduces some delay (e.g., shown in FIG. 2 as td2 or 1/2 of td1), the even numbered and odd numbered series arrangements generate clock signals having different delays relative to the input clock signal clk_in. In other words, the first clock signal CLK is delayed by two units of inverter delay, while the second clock signal, clk_b is delayed by three units of inverter delay. For this reason, as shown in FIG. 2, although first and second clock signals clk and clk_b each have a phase equal to the phase of the input signals clk_in, first and second clock signals clk and clk_b are not synchronous with each other. This timing mismatch is not easily corrected during the phase splitter fabrication.